In the field of this invention that high frequency voltage controlled oscillators are commonly used in RF (Radio Frequency) circuit design. The standard ‘harmonic oscillator’ used in this invention is well known in the literature. However this invention addresses the problems of operating the circuit at low voltage (required for modern CMOS chips) and provides a technique for biasing the output so that it can be conveniently used by following circuitry.
From U.S. Pat. No. 6,225,871 there is known a voltage controlled CMOS oscillator in which the frequency of oscillation of two cross-coupled CMOS inverters with a parallel LC tank circuit connected between the two drains can be varied by a control voltage which varies the capacitance of the tank circuit. However, since the supply to the oscillator is used to tune the oscillator, the connection of a following stage to the oscillator is compromised, the tuning of the oscillator is subject to noise in the supply, and the oscillator supply is not easily decoupled from the chip supply.
From U.S. Pat. No. 6,281,758 there is known a differential LC-based voltage-controlled CMOS oscillator with a charge pump and loop filter architecture. However, this oscillator is susceptible to noise in the power supply. Also, the connection of a following stage to the oscillator compromises the working point of the oscillator.
From U.S. Pat. No. 6,087,896 there is known a capacitive compensation technique using MOS capacitance.
Further, known voltage controlled CMOS oscillators suffer one or more of the following disadvantages:                difficulty of implementation at low supply voltage (e.g., 1.8V)        difficulty of coupling oscillator output into a following stage (as, for example, mentioned above)        difficulty of achieving a required tuning range with a reduced supply voltage.        
A need therefore exists for a voltage controlled oscillator circuit wherein the abovementioned disadvantage(s) may be alleviated.